1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to the fabrication of horizontal chalcogenide memory devices.
2. Description of Related Art
Electrically writable and erasable phase change materials have traditionally been used for memory devices. Chalcogenide materials can be electrically switched between two structural states of generally crystalline and generally amorphous local order. The generally crystalline state is a phase in which the material's atoms and/or electrons form a repeatable lattice structure, whereas the atoms and/or electrons of the generally amorphous state are randomly distributed. The structural state can also be switched among a range of detectable structural states of local order between the extremes of completely crystalline and completely amorphous states.
The currently favored chalcogenide materials that are used for phase change memory applications typically contain mixtures of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, and/or O. Because of the range of structural states, a given as-deposited stoichiometric chalcogenide material can have varied bulk conductivities. Generally speaking, the more crystalline local order the state has, the higher the conductivity of the material. Moreover, the conductivity of the material can be selectively and repeatably established via an electrical pulse of given voltage and duration, herein called a setting or resetting voltage. The conductivity remains stable until another setting or resetting voltage of comparable size is applied. Furthermore, the conductivity of the material appears to vary inversely with the setting or resetting voltage and does not depend upon the previous state of the material, i.e., the material lacks hysteresis. The aforementioned materials can be used to store and retrieve information within a non-volatile, overwritable memory cell. When different setting or resetting voltages are employed to change the conductivity of the material, the corresponding conductivities can be distinguished by various means including, but not limited to, the application of a relatively smaller voltage across the material within the cell. If, for example, two distinct setting or resetting voltages are used, one memory cell is able to store and retrieve one bit of binary encoded data. If more than two distinct setting or resetting voltages are used, then one memory cell is able to store and retrieve an analog form that can represent multiple bits of binary encoded data. Since the chalcogenide materials are able to maintain their respective conductivities, the memory cells are non-volatile, in that no refreshes are necessary to keep the data stored. Because for example the same materials lack hysteresis, the memory cells can be directly overwritten, in that no data erasures are necessary prior to storing new data within the cells.
It is known that chalcogenide phase change memory is not easy to incorporate into a CMOS circuit because the chalcogenide material requires a relatively high current to change its state. Reducing the cross-sectional area of the chalcogenide part can reduce the current requirement in direct proportion. Structures which have been developed and which reduce this cross-sectional area involve fabricating ultra small contacts and depositing the chalcogenide into the contacts. One of the methods of fabricating ultra small contacts involves using a dielectric film to further reduce the photolithographic limit as referenced in U.S. Pat. No. 6,111,264. The cross-sectional area can be reduced, but the shrinking ratio is limited by the spacer thickness. For example, if the pore diameter is 1600 Å and the spacer thickness is 400 Å, the shrinkage ratio is only about 50%. The minimum pore diameter is determined by the photolithography and the spacer thickness shrinkage ratio can be limited. Thus, it can be difficult to scale down the chalcogenide parts in this fashion. If the chalcogenide parts cannot be scaled down, the current must be high for them to change their states.
There can be additional problems once the pores are scaled down. For instance, the uniformity of the pore-to-pore diameters can be poor. Moreover, the small pores can place constraints on the chalcogenide deposition process since it will be more difficult to deposit materials into the tiny openings. For example, in the context of pores formed using the process of the preceding paragraph, overhang of the spacer may partially or fully occlude the pore, further compromising the reliability of the deposition procedure. Additionally, if the bottoms of the pores receive poor bottom coverage, the electrodes beneath them would not be able to predictably change the phases of the chalcogenide parts. If the phases are not repeatable when a given current is applied, the memory cell cannot reliably store data.
A need thus exists in the prior art for a robust process to form chalcogenide parts with uniformly smaller cross-sectional areas. Smaller cross-sectional areas can decrease the power requirement for the device. A further need exists for these elements to have better contacts with the bottom electrodes.